JEDEC-JESD47
Stress-Test-Driven Qualification of Integrated Circuits
Defines a stress-test-driven approach for qualifying new semiconductor technologies and products. Specifies minimum sample sizes, stress conditions, and failure criteria for reliability qualification.
- Document
- JESD47L (2022)
- URL
- https://www.jedec.org/standards-documents/docs/jesd-47
- Label
- Standard
- Keywords
- IC qualification stress testing reliability qualification sample size failure criteria semiconductor qualification JEDEC
Domain: Semiconductor and Electronics · Standard