Verilog
SystemVerilog — Unified Hardware Design, Specification, and Verification Language
IEEE standard for hardware design, simulation, and verification. Extends Verilog with classes, assertions, coverage, and constrained randomisation. The dominant HDL in the semiconductor industry for ASIC and FPGA development.
- Document
- IEEE 1800-2023
- URL
- https://standards.ieee.org/ieee/1800/7702/
- Label
- Standard
- Keywords
- SystemVerilog Verilog ASIC FPGA hardware verification assertions coverage semiconductor design
Domain: Programming Languages · Standard